JGS has an immediate need for an Engineer to support our client’s development of custom imagers for various government programs. The Engineer will work closely with the design team to assist with the pre-silicon and post-silicon verification of digital ASICs designed in an advanced node process.
- Proficient in Verilog
- Extensive experience with HDL simulators (i.e. Incisive, Modelsim/Questa/VCS, etc)
- Testbench development
- Running simulations to verify ASIC functionality and timing closure.
- Creating test vectors (post tape-out)
- Working with test engineers to analyze test results
- Use of scripting to automate test execution
- FPGA design/programming experience (Xilinx preferred)
- Familiarity with microprocessor architectures
- Familiarity with test vector generation and automatic test equipment (ATEs)
- System Verilog, UVM
- Static timing analysis
PhD plus 5 years minimum experience, or MS plus 8 years
minimum experience or BS plus 10 year minimum experience