Senior DFT Engineer:
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today.
Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Design-for-Test Engineering team at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. If you're creative and autonomous, we want to hear from you! At NVIDIA, you will have the opportunity to shape some of the most incredible products on the market today from products like DGX-1, P100, the Shield to Tesla for Data Centers. Your work will touch every industry - from medical, to auto, to robotics and more.
What you'll be doing:
- As a member in our team, you will own and work with multi-functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression.
- You will help develop and deploy DFT methodologies for our next generation products.
- You will also help mentor junior engineers on test designs and trade-offs including cost and quality.
What we need to see:
- BSEE with 8+, MSEE with 5+ years of experience or PhD in DFT or related domains
- You will have a solid knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation
- You will possess excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools
- You will also have good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs
- Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development
- Strong programming and scripting skills in Perl, Python or Tcl desired
- Exceptional written and oral and interpersonal skills with the curiosity to work on rare challenges